In memory devices, equalization circuits are used to pre-charge bitlines and data lines. Equalization circuits are also used to automatically power down circuitry after a cycle is completed in order to save power (i.e. the wordline may be switched off after a read access if the data is stored in a register).
Traditional uses of equalization circuits allow pre-charge of the data path, and automatic power down after the completion of a cycle. However, during equalization, the memory cell is "fighting" against the equalization circuitry on the bitlines. Such fighting can cause a "crow-bar" current as high as several mA during the equalization time period. Second, should the address change cause a new wordline to be selected before equalization has pulled the bitlines to a high enough level, the contents of the newly selected cell can be overwritten. Such a condition is known as read disturb or write disturb (depending on the cycle that causes the problem). The use of a register in the data path so that the wordlines can be turned off after a read cycle, creates an additional critical timing relationship. The register must be clocked during the time when correct data is available from the memory cell no matter what the relationship of the address signals. This can be a difficult condition to satisfy over all process corners, voltages, and temperatures.